Editing arm holdings/microarchitectures/cortex-a53

{{armh title|Cortex-A53|arch}}
{{microarchitecture
|atype=CPU
|name=Cortex-A53
|designer=ARM Holdings
|manufacturer=TSMC
|manufacturer 2=Samsung
|manufacturer 3=GlobalFoundries
|Max clock rate=2,45GHz boost
|introduction=October 30, 2012
|process=40 nm
|process 2=28 nm
|process 3=20 nm
|process 4=16 nm
|process 5=14 nm
|process 6=10 nm
|cores=1
|cores 2=2
|cores 3=3
|cores 4=4
|type=In-order
|oooe=No
|speculative=Yes
|renaming=No
|stages=8
|decode=2-way
|isa=ARMv8
|feature=Hardware virtualization
|extension=FPU
|extension 2=NEON
|extension 3=TrustZone
|l1i=8-64 KiB
|l1i per=core
|l1i desc=2-way set associative
|l1d=8-64 KiB
|l1d per=core
|l1d desc=4-way set associative
|l2=128 KiB - 2 MiB
|l2 per=cluster
|l2 desc=16-way set associative
|predecessor=Cortex-A7
|predecessor link=arm_holdings/microarchitectures/cortex-a7
|successor=Cortex-A55
|successor link=arm_holdings/microarchitectures/cortex-a55
|pipeline=Yes
|issues=2
|core names=<!-- Yes if specify -->
}}
'''Cortex-A53''' (formerly '''Apollo''') is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A7|l=arch}}. The Cortex-A53, which implemented the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}} or {{armh|Cortex-A72|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance.

Note that this microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.

== Process Technology ==
{{empty section}}

== Compiler support ==
{| class="wikitable"
|-
! Compiler !! Arch-Specific || Arch-Favorable || Arch-Target
|-
| [[GCC]] || <code>-march=armv8-a</code> || <code>-mtune=cortex-a53</code> || <code>-mcpu=cortex-a53</code>
|-
| [[LLVM]] || <code>-march=armv8-a</code> || <code>-mtune=cortex-a53</code> || <code>-mcpu=cortex-a53</code>
|}

Note that for big.LITTLE systems it's possible to specify more specific performance tunes:

* <code>-mtune=cortex-a57.cortex-a53</code>
* <code>-mtune=cortex-a72.cortex-a53</code>
* <code>-mtune=cortex-a73.cortex-a53</code>



== Architecture ==
=== Key changes from {{\\|Cortex-A15}} ===
{{empty section}}
=== Block Diagram ===
{{empty section}}
=== Memory Hierarchy ===
{{empty section}}

== Licensees ==
Arm named the following companies as licensees.

{{collist
|count = 2
|
* [[Allwinner]] (A64, H5, H6, H64)
* [[Amlogic]] (S805X, S905, S912)
* [[AMD]]
* [[Broadcom]]
* [[Samsung]]
* [[Altera]]
* [[STMicroelectronics]]
* [[MediaTek]]
* [[Qualcomm]]
* [[Xilinx]]
}}

== Die ==
=== 20 nm ===
==== Samsung [[Exynos 5433]] ====
* Samsung [[20 nm process]]
* 113 mm² die size
* Mali-T760 (6 EU)
* Quad-core Cortex-A53 ([[small cores]])
** 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2
** 4.4 mm² per cluster
*** ~1 mm² per core
*** ~0.55 mm² for 256 KiB L2 cache
* Quad-core {{\\|Cortex-A57}} ([[big cores]])
** 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2
** 15.85 mm² per cluster
*** ~3 mm² per core
*** ~3.87 mm² for 2 MiB L2 cache


:[[File:exynos 5433 die.png|600px]]

==== MediaTek [[Helio X20]] ====

* TSMC [[20 nm process]]
* 100 mm² die size
* Quad-core ULP Cortex-A53
** ~21.81 mm² per cluster
*** ~4.23 mm² per core
* Quad-core efficient Cortex-A53
** ~29.73 mm² per cluster
*** ~5.41 mm² per core
* Dual-core High-performance {{\\|Cortex-A72}} +  1 MiB L2
** ~27.36 mm² per cluster
*** ~ 9.60 mm² per core
*** ~ 7.50 mm² for 1 MiB L2


:[[File:mt6797 die.png|600px]]

=== 16 nm ===
==== Renesas [[R-Car H3]] ====
* TSMC [[16 nm process]]
* 12.94 mm × 8.61 mm
* 111.36 mm² die size
* Quad-core Cortex-A53
** ~3.27 mm² cluster
** ~0.60 mm² core
** ~0.7`mm² L2 cache
* Quad-core {{\\|Cortex-A57}}
** ~10.21 mm² cluster
** ~1.66 mm² core
** ~3.28 mm² L2 cache
* {{\\|Cortex-R7}} (dual-core [[lock-step]])
** ~1.04 mm² cluster
* GX6650 GPU
** ~28.12 mm²


: [[File:r-car h3 die shot.png|650px]]

== All Cortex-A53 Chips ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="25">List of all Cortex-A53 Chips</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th></tr>
{{comp table header 1|cols=Launched, Designer, Family, Process, Core, C, T, L2$, L3$, Frequency, Max Mem, Designer, Name, Frequency}}
{{#ask: [[Category:all microprocessor models]] [[microarchitecture::Cortex-A53]]
 |?full page name
 |?model number
 |?first launched
 |?designer
 |?microprocessor family
 |?process
 |?core name
 |?core count
 |?thread count
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?max memory#GiB
 |?integrated gpu designer
 |?integrated gpu
 |?integrated gpu base frequency
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=15
 |mainlabel=-
 |limit=100
 |valuesep=,
}}
{{comp table count|ask=[[Category:all microprocessor models]] [[microarchitecture::Cortex-A53]]}}
</table>
{{comp table end}}

== Bibliography ==
* Pyo, Jungyul, et al. "23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015
* Mair, Hugh T., et al. "4.3 A 20nm 2.5 GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.
codename	Cortex-A53 +
core count	1 +, 2 +, 3 + and 4 +
designer	ARM Holdings +
first launched	October 30, 2012 +
full page name	arm holdings/microarchitectures/cortex-a53 +
instance of	microarchitecture +
instruction set architecture	ARMv8 +
manufacturer	TSMC +, Samsung + and GlobalFoundries +
microarchitecture type	CPU +
name	Cortex-A53 +
pipeline stages	8 +
process	40 nm (0.04 μm, 4.0e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) +