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Difference between revisions of "intel/core i5/i5-8350u"
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== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type= | + | |type=DDR4-2400 |
− | |type 2= | + | |type 2=LPDDR3-2133 |
− | |||
|ecc=No | |ecc=No | ||
|max mem=32 GiB | |max mem=32 GiB | ||
|controllers=1 | |controllers=1 | ||
|channels=2 | |channels=2 | ||
− | |max bandwidth= | + | |max bandwidth=35.76 GiB/s |
− | |bandwidth schan= | + | |bandwidth schan=17.88 GiB/s |
− | |bandwidth dchan= | + | |bandwidth dchan=35.76 GiB/s |
}} | }} | ||
Revision as of 05:18, 21 August 2017
Template:mpu Core i5-8350U is a 64-bit quad-core performance x86 mobile microprocessor introduced by Intel in mid-2017. This processor, which is based on an enhanced version of the Kaby Lake microarchitecture, is manufactured on Intel's 2nd generation enhanced 14nm+ process. The i5-8350U operates at 1.7 GHz with a TDP of 15 W and Turbo Boost frequency of up to 3.6 GHz. This MPU supports up to 32 GiB of dual-channel DDR4-2400 memory.
Cache
- Main article: Kaby Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Graphics
This section is empty; you can help add the missing info by editing this page. |
Features
[Edit/Modify Supported Features]
Facts about "Core i5-8350U - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i5-8350U - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology + and My WiFi Technology + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel my wifi technology support | true + |
has intel secure key technology | true + |
has intel smart response technology support | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel turbo boost technology 2 0 | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 12 + |
supported memory type | DDR4-2400 + and LPDDR3-2133 + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |