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Revision as of 12:23, 7 December 2018
Edit Values | |
Kirin 970 | |
General Info | |
Designer | HiSilicon, ARM Holdings |
Manufacturer | TSMC |
Model Number | 970 |
Part Number | Hi3670 |
Market | Mobile |
Introduction | September 1, 2017 (announced) September 1, 2017 (launched) |
General Specs | |
Family | Kirin |
Series | 900 |
Frequency | 1,800 MHz, 2,360 MHz |
Microarchitecture | |
ISA | ARMv8 (ARM) |
Microarchitecture | Cortex-A53, Cortex-A73 |
Core Name | Cortex-A53, Cortex-A73 |
Process | 10 nm |
Transistors | 5,500,000,000 |
Technology | CMOS |
Die | 96.72 mm² 9.75 mm × 9.92 mm |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Max Memory | 8 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Kirin 970 is a 64-bit octa-core high-performance mobile ARM LTE SoC introduced by HiSilicon in mid-2017 at the 2017 IFA. This chip, which is fabricated on a 10 nm process, features four Cortex-A73 big cores operating at up to 2.36 GHz along with four Cortex-A53 little cores operating at up to 1.8 GHz. The 970 incorporates ARM's Mali G72 (12 core) IGP operating at 850 MHz and supports up to 8 GiB of quad-channel LPDDR4X-3732 memory.
Contents
Overview
Introduced at the 2017 IFA, the overall core organization is identical to the Kirin 960 which was introduced the previous year, but features 20% power efficiency and 40% smaller die area due to the process shrink. The 970 ballooned to over 37.5% more transistors from 4 billion in the 960 to 5.5 billion. The 970 adds many enhancements, including a more powerful Mali G72 GPU and incorporates a new Neural Network Processing Unit (NPU) designed for AI acceleration. The 970 has two improved ISPs and a more powerful LTE modem supporting up to User Equipment (UE) category 18 capable of reaching a maximum downlink of 1.2 Gbps (4x4 MIMO, 256 QAM, 3CC CA).
Cache
- Main articles: Cortex-A53 § Cache and Cortex-A73 § Cache
For the Cortex-A73:
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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For the Cortex-A53:
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
The Kirin 970 supports 4-channel LPDDR4X up to 1866 MHz. Each channel supports at most two ranks.
Integrated Memory Controller
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Graphics
Integrated Graphics Information
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Hardware Accelerated Video Capabilities | |||||||
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Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | ✘ | Main | High | 1080p (1920 x 1080) 80 Mbit/s or 60 fps | |||
MPEG-4 AVC (H.264) | Baseline, High | 5.1 | 3840×2160 720p@240 fps |
High | 5.0 | 4K x 2K (3840 x 2160) 135 Mbit/s or 4K x 2K@30 fps | |
HEVC (H.265) | Main | Main | 3840×2160 720p@240 fps |
Main | 5.1 | 4K x 2K (3840 x 2160) 160 Mbit/s or 4K x 2K@60 fps | |
VC-1 | ✘ | Simple, Main, Advanced | M, H, 3 | 1080p (1920 x 1080) 45 Mbit/s or 60 fps | |||
VP6 | ✘ | 1080p (1920 x 1080) 50 Mbit/s or 60 fps | |||||
VP8 | ✘ | 1080p (1920 x 1080) 50 Mbit/s or 60 fps | |||||
VP9 | ✘ | 2 | 4K x 2K (3840 x 2160) 100 Mbit/s or 4K x 2K@60 fps |
Wireless
- LTE Modem
- Up to User Equipment (UE) category 18
- Downlink of up to 1.2 Gbps (4x4 MIMO, 256 QAM, 3CC CA)
- Uplink of up to 150 Mbps (2x20MHz CA, 64-QAM)
- Up to User Equipment (UE) category 18
- Wi-Fi 802.11 ac Dual Band
- Bluetooth 4.2
- NFC
- GPS / A-GPS / GLONASS / BDS
Expansions
- Dual ISPs
- 14-bit
Neural Network Processing Unit (NPU)
The Kirin 970 incorporates a new Neural Network Processing Unit (NPU) designed specifically to be used as an AI accelerator. According to CEO Richard Yu, who also introduced the processor at 2017 IFA, the NPU uses up the die area of roughly half of the CPU while consuming 50% less power and performing around 25 times faster than a traditional CPU for tasks such as photo recognition. The NPU is said to deliver 1.92 TFLOPs (HP 16-bit) through 256 MAC/cycleS. While the exact architectural details of the NPU have been withheld, the NPU appear to be a licensed IP design from Cambricon Technologies.
Utilizing devices
- Huawei Mate 10
- Huawei Mate 10 Pro
- Huawei Mate 10 Porsche Design
- Huawei P20
- Huawei Mate RS Porsche Design
- Honor V10 (Honor View 10)
- Honor 10
- Honor Play
- Huawei Nova 3
- Honor Note 10
- Xiaomi Mi 8 EE
- Huawei P20 Pro
This list is incomplete; you can help by expanding it.
Documents
Bibliography
- Huawei Kirin 970 Keynote, 2017 IFA
- all microprocessor models
- microprocessor models by hisilicon
- microprocessor models by hisilicon based on cortex-a53
- microprocessor models by hisilicon based on cortex-a73
- microprocessor models by arm holdings
- microprocessor models by arm holdings based on cortex-a53
- microprocessor models by arm holdings based on cortex-a73
- microprocessor models by tsmc
base frequency | 1,800 MHz (1.8 GHz, 1,800,000 kHz) + and 2,360 MHz (2.36 GHz, 2,360,000 kHz) + |
core count | 8 + |
core name | Cortex-A53 + and Cortex-A73 + |
designer | HiSilicon + and ARM Holdings + |
die area | 96.72 mm² (0.15 in², 0.967 cm², 96,720,000 µm²) + |
die length | 9.75 mm (0.975 cm, 0.384 in, 9,750 µm) + |
die width | 9.92 mm (0.992 cm, 0.391 in, 9,920 µm) + |
family | Kirin + |
first announced | September 1, 2017 + |
first launched | September 1, 2017 + |
full page name | hisilicon/kirin/970 + |
has ecc memory support | false + |
instance of | microprocessor + |
integrated gpu | Mali-G72 + |
integrated gpu base frequency | 850 MHz (0.85 GHz, 850,000 KHz) + |
integrated gpu designer | ARM Holdings + |
integrated gpu execution units | 12 + |
isa | ARMv8 + |
isa family | ARM + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + and 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + and 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + and 128 KiB (131,072 B, 0.125 MiB) + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + and 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
ldate | September 1, 2017 + |
main image | + |
manufacturer | TSMC + |
market segment | Mobile + |
max cpu count | 1 + |
max memory | 8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) + |
max memory bandwidth | 27.82 GiB/s (28,487.68 MiB/s, 29.871 GB/s, 29,871.498 MB/s, 0.0272 TiB/s, 0.0299 TB/s) + |
max memory channels | 4 + |
microarchitecture | Cortex-A53 + and Cortex-A73 + |
model number | 970 + |
name | Kirin 970 + |
part number | Hi3670 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |
series | 900 + |
smp max ways | 1 + |
supported memory type | LPDDR4X-3732 + |
technology | CMOS + |
thread count | 8 + |
transistor count | 5,500,000,000 + |
used by | Huawei Mate 10 +, Huawei Mate 10 Pro +, Huawei Mate 10 Porsche Design +, Huawei P20 +, Huawei Mate RS Porsche Design +, Honor V10 (Honor View 10) +, Honor 10 +, Honor Play +, Huawei Nova 3 +, Honor Note 10 +, Xiaomi Mi 8 EE + and Huawei P20 Pro + |
word size | 64 bit (8 octets, 16 nibbles) + |