Information for "socionext/sc2a11"

Basic information

Display title	SC2A11 - Socionext
Default sort key	SC2A11, socionext
Page length (in bytes)	1,632
Page ID	11904
Page content language	English (en)
Page content model	wikitext
Indexing by robots	Allowed
Number of redirects to this page	4
Counted as a content page	Yes
Number of subpages of this page	0 (0 redirects; 0 non-redirects)

Edit	Allow all users (infinite)
Move	Allow all users (infinite)

Page creator	Inject (talk \| contribs)
Date of page creation	03:09, 4 December 2016
Latest editor	93.218.254.190 (talk)
Date of latest edit	15:00, 15 February 2019
Total number of edits	26
Total number of distinct authors	5
Recent number of edits (within past 90 days)	0
Recent number of distinct authors	0

Transcluded templates (13)	Templates used on this page: Template:arch (view source) (protected) Template:armh (edit) Template:cache size (view source) (protected) Template:chip (view source) (protected) Template:expansions (edit) Template:istrue (view source) (protected) Template:link-armh (edit) Template:main (view source) (protected) Template:memory controller (edit) Template:socionext title (edit) Template:url parse anchor (view source) (protected) Template:url parse article (view source) (protected) Module:chip (view source)

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	SC2A11 - Socionext#io +
base frequency	1,000 MHz (1 GHz, 1,000,000 kHz) +
bus type	AMBA +
core count	24 +
core name	Cortex-A53 +
designer	Socionext + and ARM Holdings +
first announced	November 14, 2016 +
first launched	2017 +
full page name	socionext/sc2a11 +
has ecc memory support	true +
instance of	microprocessor +
isa	ARMv8 +
isa family	ARM +
l1$ size	1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description	4-way set associative +
l1d$ size	768 KiB (786,432 B, 0.75 MiB) +
l1i$ description	2-way set associative +
l1i$ size	768 KiB (786,432 B, 0.75 MiB) +
l2$ description	16-way set associative +
l2$ size	3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
l3$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldate	3000 +
main image	+
market segment	Server +, Networking + and IoT +
max cpu count	64 +
max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth	31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels	2 +
max pcie lanes	4 +
microarchitecture	Cortex-A53 +
model number	SC2A11 +
name	Socionext SC2A11 +
smp max ways	64 +
supported memory type	DDR4-2133 +
tdp	5 W (5,000 mW, 0.00671 hp, 0.005 kW) +
technology	CMOS +
thread count	24 +
word size	64 bit (8 octets, 16 nibbles) +