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Exynos M2 - Microarchitectures - Samsung
Edit Values | |
Mongoose 2 µarch | |
General Info | |
Arch Type | CPU |
Designer | Samsung |
Manufacturer | Samsung |
Introduction | February 23, 2017 |
Phase-out | 2018 |
Process | 10 nm |
Core Configs | 4 |
Pipeline | |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 14 |
Decode | 4-way |
Instructions | |
ISA | ARMv8 |
Cache | |
L1I Cache | 64 KiB/core 4-way set associative |
L1D Cache | 32 KiB/core 8-way set associative |
L2 Cache | 2 MiB/cluster 16-way set associative |
Succession | |
Exynos Mongoose 2 (M2) is the successor to the Mongoose 1, a 10 nm ARM microarchitecture designed by Samsung for their consumer electronics.
Contents
Process Technology[edit]
M2 was fabricated on Samsung's first generation 10LPE (Low Power Early) process.
Compiler support[edit]
Compiler | Arch-Specific | Arch-Favorable |
---|---|---|
GCC | -mcpu=exynos-m1 |
-mtune=exynos-m1
|
LLVM | -mcpu=exynos-m2 |
-mtune=exynos-m2
|
Architecture[edit]
Key changes from Mongoose 1[edit]
- 10nm (10LPE) process (from 14 nm)
- Larger ROB (100, up from 96)
This list is incomplete; you can help by expanding it.
Block Diagram[edit]
Core Cluster Overview[edit]
(Cluster identical to Mongoose 1)
Individual Core[edit]
Memory Hierarchy[edit]
- Cache
- L1I Cache
- 64 KiB, 4-way set associative
- 128 B line size
- per core
- Parity-protected
- 64 KiB, 4-way set associative
- L1D Cache
- 32 KiB, 8-way set associative
- 64 B line size
- per core
- 4 cycles for fastest load-to-use
- 16 B/cycle load bandwidth
- 16 B/cycle store bandwidth
- 32 KiB, 8-way set associative
- L2 Cache
- 2 MiB, 16-way set associative
- 4x banks (512 KiB each)
- Inclusive of L1
- 22 cycles latency
- 16 B/cycle/CPU bandwidth
- 2 MiB, 16-way set associative
- L1I Cache
The M2 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
- TLBs
- ITLB
- 256-entry
- DTLB
- 32-entry
- STLB
- 1,024-entry
- Per core
- ITLB
- BPU
- 4K-entry main BTB
- 64-entry µBTB
- 64-entry return stack
- 8K-entry L2 BTB
Core[edit]
The M2 core is almost identical to the M1.
All M2 Processors[edit]
List of M2-based Processors | ||||||||
---|---|---|---|---|---|---|---|---|
Main processor | Integrated Graphics | |||||||
Model | Family | Launched | Arch | Cores | Frequency | Turbo | GPU | Frequency |
Count: 0 |
Facts about "Exynos M2 - Microarchitectures - Samsung"
codename | Mongoose 2 + |
core count | 4 + |
designer | Samsung + |
first launched | February 23, 2017 + |
full page name | samsung/microarchitectures/m2 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | Samsung + |
microarchitecture type | CPU + |
name | Mongoose 2 + |
phase-out | 2018 + |
pipeline stages | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |